RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

ANTOLA, ANNA MARIA
 Distribuzione geografica
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Continente #
NA - Nord America 2.288
EU - Europa 713
AS - Asia 131
AF - Africa 3
Continente sconosciuto - Info sul continente non disponibili 3
OC - Oceania 2
SA - Sud America 2
Totale 3.142
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Nazione #
US - Stati Uniti d'America 2.225
UA - Ucraina 154
SE - Svezia 124
IT - Italia 91
AT - Austria 66
CA - Canada 63
DE - Germania 62
VN - Vietnam 60
FI - Finlandia 58
GB - Regno Unito 48
ES - Italia 37
CN - Cina 36
IE - Irlanda 29
IN - India 16
NL - Olanda 15
BE - Belgio 12
JO - Giordania 12
FR - Francia 6
GR - Grecia 6
TR - Turchia 5
EU - Europa 3
RU - Federazione Russa 3
KR - Corea 2
MU - Mauritius 2
PL - Polonia 2
AU - Australia 1
BR - Brasile 1
CI - Costa d'Avorio 1
NZ - Nuova Zelanda 1
PY - Paraguay 1
Totale 3.142
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Città #
Woodbridge 335
Fairfield 298
Ann Arbor 214
Chandler 210
Houston 196
Ashburn 141
Wilmington 131
Seattle 120
Jacksonville 91
Cambridge 80
Vienna 66
Dearborn 58
Ottawa 56
Lawrence 45
Málaga 37
Medford 33
Des Moines 31
Dublin 29
Dong Ket 21
Beijing 20
San Diego 20
Milan 16
Amsterdam 14
Helsinki 13
Amman 12
Brussels 12
New York 12
Princeton 12
London 6
North York 6
Auburn Hills 5
Falls Church 5
Norwalk 5
Boardman 4
Miami 4
Nanjing 4
Washington 4
Indiana 3
Izmir 3
Los Angeles 3
Mountain View 3
Redwood City 3
Verona 3
Guangzhou 2
Hefei 2
Kunming 2
Palazzolo 2
Warsaw 2
Abidjan 1
Ajax 1
Atlanta 1
Chengdu 1
Erding 1
Florence 1
Hamilton 1
Hanover 1
Hounslow 1
Jinan 1
Kumar 1
Lanzhou 1
Modena 1
Ningbo 1
San Francisco 1
Seongnam 1
Shanghai 1
Southwark 1
Sunshine Coast 1
São Paulo 1
Williamston 1
Xian 1
Totale 2.416
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Nome #
An Approach to Fault Tolerance In Architectures for Discrete Fourier Transforms 127
Parallel architectures for elliptic curve cryptoprocessors over binary extension fields 103
A Chip-set for the Generalized Hough Transform 99
GINGER: a minimizing-effects reprogramming paradigm for distributed sensor networks 98
Two-dimensional object recognition on parallel machines 96
A novel hardware/software codesign methodology based on dynamic reconfiguration with ImpulseC and CoDeveloper 94
High level synthesis through folding of data flow graphs: optimal intra-node scheduling 93
Designing and testing of a microprogrammed fault tolerant CPU 92
The hArtes Tool Chain 90
Balancing of fault tolerance in the new version of the FERMI channel chip: a functional evaluation 89
Definition and evaluation of a transputer-based architecture for image compression and reconstruction 88
Fault-tolerance in FFT Arrays: Time Redundancy Approaches 87
Evaluation of FERMI readout of the ATLAS tilecal prototype 83
Semiconcurrent error detection in data paths 81
Evolvable Hardware: a Functional Level Evolution Framework based on Impulse C 80
Tolerance to transient faults in microprogrammed control units 79
A model for the evaluation of fault tolerance in the FERMI system 77
Fault Tolerance in FFT Arrays: Time redundancy Approaches 77
Arrays for digital signal processing functions: fault tolerance and functional reconfiguration 76
High level architectural synthesis: precedence analysis ad automatic cycle detection 74
Modular design methodologies for image processing architectures 71
Policies for fault-tolerance through mixed space- and time- redundancy in semi-systolic FFTs arrays 70
Window-based dedicated parallel architectures for image processing 69
High-Level Synthesis of Data Paths with Concurrent Error Detection 68
Testing and Diagnosis of FFT Arrays 66
Fault identification and fault location in algorithmic flow-driven WSI architectures 66
Transient Fault Management in Systems Based on the AMD 2900 Microprocessors 64
Reconfiguration of binary trees: the flow-driven approach 63
A transputer-based self-tuning edge detection chain 63
Testing approaches for flow graph derived FFTs arrays 63
Semi-Concurrent Error Detection in Data Paths 61
Multiple-Transform Pipelines for Image Coding 60
Modular design methodologies for image processing architectures 60
Dedicated circuits for the generation of windows in image processing architectures 58
DFGs for Synthesis of Alternatives Architectures: Node Activation Synthesis 57
Window-based functional blocks for image processing 55
On-line Dignosis and Reconfiguration of FPGA Systems 52
Concurrent Programming Robustness 48
SAR Real-Time On-Board Processing: the Architecture 45
Optimal Balancing of Acyclic and Cyclic Data Flow Graphs in High Level Architectural Synthesis 42
The Flexibly Dedicated Approach: Reconfigurable Arrays for Low-Level Image Processing 42
Backward Error Recovery in Concurrent Environment 41
Radix-r Implementation of Neural Nets 37
Transient Fault Management in Microprogrammed Units: a Software Recovery Approach 36
Optimizing High-Level Synthesis for Self-Checking Arithmetic Circuits 33
Two-dimensional object recognition on parallel machines 4
Totale 3.177
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Categoria #
all - tutte 9.240
article - articoli 3.162
book - libri 0
conference - conferenze 5.640
curatela - curatele 0
other - altro 0
patent - brevetti 0
selected - selezionate 0
volume - volumi 438
Totale 18.480
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Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019279 0 0 0 0 0 0 0 0 0 67 113 99
2019/2020764 43 42 12 53 90 102 98 62 95 29 113 25
2020/2021476 45 12 81 24 35 38 32 50 27 31 29 72
2021/2022335 18 42 20 4 43 15 27 17 13 13 41 82
2022/2023427 59 50 14 38 40 75 0 21 64 42 19 5
2023/2024120 10 35 5 14 8 29 13 4 0 2 0 0
Totale 3.177