A prototype of the “Channel chip” of the FERMI microsystem has been designed and fabricated (version 1, 1994), being currently under test (1995-96). Future implementations (version 11, 1996) require a structural refinement and a reduction of dimension of the chip. These modifications require in turn a redistribution and a redesign of the implemented fault tolerance features. In this paper guide-lines for this task are presented and a proposal is discussed.

Balancing of fault tolerance in the new version of the FERMI channel chip: a functional evaluation

ANTOLA, ANNA MARIA;BREVEGLIERI, LUCA ODDONE
1996-01-01

Abstract

A prototype of the “Channel chip” of the FERMI microsystem has been designed and fabricated (version 1, 1994), being currently under test (1995-96). Future implementations (version 11, 1996) require a structural refinement and a reduction of dimension of the chip. These modifications require in turn a redistribution and a redesign of the implemented fault tolerance features. In this paper guide-lines for this task are presented and a proposal is discussed.
Proceedings of the International Symposium on Defect and Fault Tolerance in VLSI Systems 1996
0818675454
INF; VLSI; calorimetry; LHC; FERMi project; RD16; CERN; fault tolerance
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/569779
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