The general trend of the hardware implementation of elliptic curve cryptography is to increase throughput by designing a variety of algorithms for the kP operation, by optimizing the architectures of the finite field basic operations, and by selecting the most appropriate coordinate system. Point addition and doubling leave few possibilities for parallelism when considering a single kP operation. It is however possible to explore the design space of an elliptic curve cryptoprocessor sharing the field operators among the computations of some different kP operations. In this paper, an analysis of various parallelism schemes is carried on. The obtained parallelism schemes are evaluated with respect to time performance, referring to an effective VLSI technology.

Parallel architectures for elliptic curve cryptoprocessors over binary extension fields

ANTOLA, ANNA MARIA;BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;MAISTRI, PAOLO
2003

Abstract

The general trend of the hardware implementation of elliptic curve cryptography is to increase throughput by designing a variety of algorithms for the kP operation, by optimizing the architectures of the finite field basic operations, and by selecting the most appropriate coordinate system. Point addition and doubling leave few possibilities for parallelism when considering a single kP operation. It is however possible to explore the design space of an elliptic curve cryptoprocessor sharing the field operators among the computations of some different kP operations. In this paper, an analysis of various parallelism schemes is carried on. The obtained parallelism schemes are evaluated with respect to time performance, referring to an effective VLSI technology.
Proceedings of the 46th IEEE Midwest Symposium on Circuits and Systems - MWSCAS 2003
0780382943
INF; cryptography; elliptic curves; parallel architecture; binary field
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/270345
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