A Low Jitter Fractional-N Digital PLL Using a Supply-Insensitive Variable-Slope DTC

This work presents a fractional- N digital phase-locked loop (PLL) featuring a supply-insensitive variable-slope digital-to-time converter (SI-VS-DTC). The proposed architecture neutralizes DTC supply sensitivity—a primary bottleneck for high-performance frequency synthesis in noisy environments—without compromising inherent linearity or baseline noise. Robust background calibration algorithms are deployed to ensure stable technique operation across process, voltage, and temperature (PVT) variations. Implemented in 28-nm CMOS, the prototype synthesizes an 8.85–10.25 GHz output from a 150-MHz reference clock, occupying an active area of 0.28 mm2 while consuming 22.5 mW. Under a 10-mVpp sinusoidal ripple or 6.2-mVrms wideband noise applied directly to the DTC supply voltage, the PLL maintains an integrated rms jitter below 69 fs and spurious tones below −62 dBc at 8.85-GHz near-integer channels.