REDAELLI, FRANCESCO
REDAELLI, FRANCESCO
DIPARTIMENTO DI ELETTRONICA E INFORMAZIONE (attivo dal 01/01/1900 al 31/12/2012)
A Design Workflow for Dynamically Recongurable Multi-FPGA Systems
2010-01-01 Alessandro, Panella; Santambrogio, MARCO DOMENICO; Redaelli, Francesco; Cancare', Fabio; Sciuto, Donatella
A Reconguration-aware Floorplacer for FPGAs
2008-01-01 Montone, Alessio; Redaelli, Francesco; Santambrogio, MARCO DOMENICO; S., Ogrenci Memik
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures
2009-01-01 Redaelli, Francesco; Santambrogio, MARCO DOMENICO; S., Ogrenci Memik
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures
2008-01-01 Redaelli, Francesco; Santambrogio, MARCO DOMENICO; S., Ogrenci Memik
Floorplacement for Partial Reconfigurable FPGA-Based Systems
2011-01-01 A., Montone; M., Santambrogio; Redaelli, Francesco; Sciuto, Donatella; Santambrogio, MARCO DOMENICO
Optimizing the demand captured by a railway system with a regular timetable
2011-01-01 Cordone, Roberto; Redaelli, Francesco
Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs
2009-01-01 R., Cordone; Redaelli, Francesco; M. A., Redaelli; Santambrogio, MARCO DOMENICO; Sciuto, Donatella
Scheduling and 2D Placement Heuristics for Partially Reconfigurable Systems
2009-01-01 Redaelli, Francesco; Santambrogio, MARCO DOMENICO; Rana, Vincenzo; S., Ogrenci Memik
Task scheduling with conguration prefetching and anti-fragmentation techniques on dynamically recongurable systems
2008-01-01 Redaelli, Francesco; Santambrogio, MARCO DOMENICO; Sciuto, Donatella
The Shining embedded system design methodology based on self dynamic reconfigurable architectures
2008-01-01 Curino, CARLO ALDO; Rana, Vincenzo; Redaelli, Francesco; Santambrogio, MARCO DOMENICO; Sciuto, Donatella