This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologies
New erase constraint for the junction-less charge-trap memory array in cylindrical geometry
MACONI, ALESSANDRO;MONZIO COMPAGNONI, CHRISTIAN;SOTTOCORNOLA SPINELLI, ALESSANDRO;LACAITA, ANDREA LEONARDO
2013-01-01
Abstract
This paper presents a detailed simulation analysis of the erase performance of junction-less charge-trap memory arrays in the cylindrical geometry, showing that a saturation of the erased threshold voltage occurs as a result of incomplete inversion of the intercell regions when positive charge is stored in the cells. This erase saturation issue is investigated as a function of string and cell parameters, revealing lower erase capabilities for large cell-to-cell separation, small substrate radius, and small equivalent-oxide thickness of the gate stack. These results add new constraints to the design of cylindrical junction-less memory technologiesFile | Dimensione | Formato | |
---|---|---|---|
ted13_2.pdf
Accesso riservato
:
Post-Print (DRAFT o Author’s Accepted Manuscript-AAM)
Dimensione
2.24 MB
Formato
Adobe PDF
|
2.24 MB | Adobe PDF | Visualizza/Apri |
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.