We describe the digital filter section of the FERMI readout microsystem. The filter section, consisting of two separate filter blocks, extracts the pulse amplitude and time information for the first-level trigger process and performs a highly accurate energy measurement for higher-level triggering and data readout purposes. An FIR-order statistic hybrid filter structure is used to improve the amplitude extraction performance. Using a training procedure the filters are optimized to produce a precise and accurate output in the presence of electronics and pile-up noise, sample timing jitter and the superposition of high-energy pulses. As the FERMIsystem resides inside the detector where accessibility is limited, the filter implementations are presented together with fault tolerance considerations. The filter section is modelled with the VHDL hardware descriptive language and the subsystems are further optimized to minimize the system latency and circuit area.

Optimized digital feature extraction in the FERMI microsystem

BREVEGLIERI, LUCA ODDONE;DADDA, LUIGI;PIURI, VINCENZO;SAMI, MARIAGIOVANNA;STEFANELLI, RENATO;
1995

Abstract

We describe the digital filter section of the FERMI readout microsystem. The filter section, consisting of two separate filter blocks, extracts the pulse amplitude and time information for the first-level trigger process and performs a highly accurate energy measurement for higher-level triggering and data readout purposes. An FIR-order statistic hybrid filter structure is used to improve the amplitude extraction performance. Using a training procedure the filters are optimized to produce a precise and accurate output in the presence of electronics and pile-up noise, sample timing jitter and the superposition of high-energy pulses. As the FERMIsystem resides inside the detector where accessibility is limited, the filter implementations are presented together with fault tolerance considerations. The filter section is modelled with the VHDL hardware descriptive language and the subsystems are further optimized to minimize the system latency and circuit area.
INF; VLSI; LHC; calorimetry; FERMI project; RD16; CERN; digital front-end
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/569748
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