Two bit-serial convolver architectures computing serial discrete convolution are presented. Their testability characteristics are studied. A linear time complexity test procedure for both structures is developed. It is shown that functional reconfigurability of these architectures represents an advantage for testability. The test procedure is in fact based on partitioning the architectures into simpler structures and testing them separately.

Testing of serial input convolvers

BREVEGLIERI, LUCA ODDONE;DADDA, LUIGI;SCIUTO, DONATELLA
1990-01-01

Abstract

Two bit-serial convolver architectures computing serial discrete convolution are presented. Their testability characteristics are studied. A linear time complexity test procedure for both structures is developed. It is shown that functional reconfigurability of these architectures represents an advantage for testability. The test procedure is in fact based on partitioning the architectures into simpler structures and testing them separately.
1990
VLSI; testing; arithmetic; convolution; convolver; INF
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/569744
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