A novel approach is presented for complex numbers in full fractional two's complement representation. A class of multipliers is discussed and evaluated: the authors consider in particular the computational time, the throughput, and the silicon area required by a VLSI implementation. High regularity and modularity are some of the most interesting features of the architecture.

Fast pipelined multipliers for bit-serial complex numbers

BREVEGLIERI, LUCA ODDONE;PIURI, VINCENZO;SCIUTO, DONATELLA
1991-01-01

Abstract

A novel approach is presented for complex numbers in full fractional two's complement representation. A class of multipliers is discussed and evaluated: the authors consider in particular the computational time, the throughput, and the silicon area required by a VLSI implementation. High regularity and modularity are some of the most interesting features of the architecture.
COMPEURO Proceedings - ADVANCED COMPUTER TECHNOLOGY, RELIABLE SYSTEMS AND APPLICATIONS
0818621419
INF; VLSI; pipelining; arithmetic; multiplier; multiplication
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/569732
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