A novel approach is presented for complex numbers in full fractional two's complement representation. A class of multipliers is discussed and evaluated: the authors consider in particular the computational time, the throughput, and the silicon area required by a VLSI implementation. High regularity and modularity are some of the most interesting features of the architecture.
Fast pipelined multipliers for bit-serial complex numbers
BREVEGLIERI, LUCA ODDONE;PIURI, VINCENZO;SCIUTO, DONATELLA
1991-01-01
Abstract
A novel approach is presented for complex numbers in full fractional two's complement representation. A class of multipliers is discussed and evaluated: the authors consider in particular the computational time, the throughput, and the silicon area required by a VLSI implementation. High regularity and modularity are some of the most interesting features of the architecture.File in questo prodotto:
Non ci sono file associati a questo prodotto.
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
