Optimization of threshold voltage window under tunneling program/erase in nanocrystal memories

This paper analyzes solutions to improve the program/ erase (P/E) window for nanocrystal (NC) memory cells, by means of the model presented in our previous work [1]. The limited threshold voltage ( ) window typically observed in the Fowler–Nordheim (FN) programming regime for NC memories was shown to be a direct consequence of the lack of any conduction and mismatch between the tunnel and the interpoly-oxide at steady-state. This condition can be avoided when tunnel oxide conduction is due to direct tunneling, but to assure sufficiently short P/E times very thin oxides are required, sacrificing cell nonvolatility. The use of alternative materials for interpoly dielectric, gate and NC is investigated. Finally, barrier engineering is presented as a valid way to improve the available window.