One of the major concerns for the feasibility of phase-change memories is the reduction of the programming current. To this aim, several efforts have been dedicated both on cell geometry and on material engineering. This paper addresses programming-current minimization by the optimization of the cell geometry and materials, programming-current scaling, and the tradeoff between programming and readout performances of the cell. A general procedure to find the optimum-cell geometry is proposed and applied to a prototype vertical cell. Then, the evolution of program and read performances through technology nodes is analyzed by numerical simulations with the aid of an analytical model, for both the isotropic- and nonisotropic-scaling approaches. The two scaling approaches are discussed and compared in terms of program and read cell performances. Finally, material optimization is considered for further program-read improvement.

Modeling of programming and read performance in phase-change memories - Part I: cell optimization and scaling

RUSSO, UGO;IELMINI, DANIELE;REDAELLI, ANDREA;LACAITA, ANDREA LEONARDO
2008

Abstract

One of the major concerns for the feasibility of phase-change memories is the reduction of the programming current. To this aim, several efforts have been dedicated both on cell geometry and on material engineering. This paper addresses programming-current minimization by the optimization of the cell geometry and materials, programming-current scaling, and the tradeoff between programming and readout performances of the cell. A general procedure to find the optimum-cell geometry is proposed and applied to a prototype vertical cell. Then, the evolution of program and read performances through technology nodes is analyzed by numerical simulations with the aid of an analytical model, for both the isotropic- and nonisotropic-scaling approaches. The two scaling approaches are discussed and compared in terms of program and read cell performances. Finally, material optimization is considered for further program-read improvement.
Amorphous semiconductors; chalcogenide; device scaling; nonvolatile memories; phase-change memory (PCM).
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/544732
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