Reliability assessment of discrete-trap memories for NOR applications

We provide an experimental and theoretical investigation of the reliability properties of discrete-trap memories in view of their application in the NOR architecture. Charge localization at the junction edges after channel hot-electron injection is studied using bake-accelerated retention tests on both nitride and nanocrystal memory cells. Vertical and lateral charge migrations are shown to be responsible for the threshold voltage loss for both small and large reading, drain voltages. Drain disturb is shown to be comparable to state-of-art Flash cells, while highly improved drain turn on immunity is shown for both nanocrystal and nitride cells.