A new channel percolation model for VT shift in discrete-trap memories

In this work we studied the mechanisms for channel conduction in discrete-trap memories (DTMs). It is shown that the threshold voltage VT in the cell corresponds to a percolation condition in the channel, where the inverted layers connect source to drain. A numerical model is presented which is able to calculate the local profile of VT in the channel, and to evaluate the global VT in the cell according to a channel percolation condition. The model is shown to account for the size dependence of VT in DTM cells, and for the staircase charge-loss characteristics observed on ultrascaled devices. The implications of the percolation mechanism from the reliability point of view are finally discussed in details.