A 500-MS/s 12-bit Pipeline-SAR ADC Using a PVT-Robust Triple-Cascoded FIA With Virtual Supply Extension

The pipeline-successive approximation register (SAR) analog-to-digital converter (ADC) extends the energy efficiency and the scaling properties of SAR ADCs to the mediumto-high resolutions and high bandwidths typical of classical pipeline ADCs. However, the residue amplifier (RA) is often a performance and energy efficiency bottleneck, especially for highspeed designs in scaled CMOS processes. This work proposes a 3×-cascoded floating inverter amplifier (FIA) RA, powered from a low supply voltage of 1 V thanks to a virtual supply extension technique, providing a robust process, voltage, and temperature (PVT) operation without requiring analog trimming, bias, or nonlinearity calibrations, except for the linear gain. The proposed amplifier is integrated in a 500-MS/s, 12-bit pipeline-SAR ADC implemented in a 28-nm CMOS process. The prototype achieves an SNDR and an SFDR of 63.4 dB and 81.0 dBc, respectively, while dissipating 6.64 mW including the on-chip digital calibrations, resulting in a Schreier figure of merit of 169.2 dB.