Synthesis of Free-Labeled Petri Nets With Inhibitor Arcs: An Exact and Efficient Approach

This paper investigates the synthesis of free-labeled Petri nets with inhibitor arcs from prefix-closed language samples. Inhibitor arcs are crucial for capturing priority logic, such as blocking behavior, in discrete-event systems, and are therefore essential for faithful Petri net models. We formulate the synthesis problem as an integer linear program that seeks a minimum Petri net that reproduces the language samples. To improve scalability, we exploit the structure of the ILP and develop a decomposition strategy that enables exact solution through branch-and-price. The proposed approach is validated on three case studies: the classical producer–consumer system, a parallel production line, and a lab-scale LEGO manufacturing plant. The results demonstrate improved robustness and efficiency over a state-of-the-art algorithm on larger instances. This provides a practical foundation for supervisor control and digital twin development in discrete-event systems.