Due to the increasing complexity of modern integrated circuits, High-Level Synthesis (HLS) is becoming a key technology in hardware design. HLS uses optimizations to assist during design space exploration. However, some of them can introduce security weaknesses. We propose an approach that leverages static analysis to identify a class of weaknesses in HLS-generated code. We show that some of these weaknesses can be corrected through the automatic generation of HLS directives. We evaluate our approach by comparing the static analysis results with formal verification. Our results show that the static approach has the same accuracy as formal methods while being 3× to 200× faster.

Using Static Analysis for Enhancing HLS Security

Collini L.;Pilato C.;
2024-01-01

Abstract

Due to the increasing complexity of modern integrated circuits, High-Level Synthesis (HLS) is becoming a key technology in hardware design. HLS uses optimizations to assist during design space exploration. However, some of them can introduce security weaknesses. We propose an approach that leverages static analysis to identify a class of weaknesses in HLS-generated code. We show that some of these weaknesses can be corrected through the automatic generation of HLS directives. We evaluate our approach by comparing the static analysis results with formal verification. Our results show that the static approach has the same accuracy as formal methods while being 3× to 200× faster.
2024
Benchmark testing
Ciphers
Codes
Registers
Security
Space exploration
Static analysis
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1260988
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