Image processing applications are today increasingly employed in safety- and mission-critical fields for perception tasks. It is therefore vital to analyse the reliability of the designed system before its deployment and, if necessary, to adopt specific hardening techniques. In this paper we propose a cross-layer reliability evaluation framework specifically meant for image processing applications accelerated onto SRAM-based FPGAs. The framework is based on two key concepts: i) an application-level error simulation based on validated error models to speed-up execution times, and ii) an analysis of the usability of the output images based on the working scenario. Such usability analysis allows the designer to study whether the downstream system would be able to take correct decisions even if the image processing outputs are corrupted. We applied the proposed idea on a motion detection application and we compared the achieved accuracy and the required execution times with the ones of a circuit-level fault injector, here considered as a ground truth. This experiment highlighted an accuracy comparable with the one of the fault injection with a dramatic time saving.

Usability-based Cross-Layer Reliability Evaluation of Image Processing Applications

Bolchini, Cristiana;Cassano, Luca;Mazzeo, Andrea;Miele, Antonio
2021

Abstract

Image processing applications are today increasingly employed in safety- and mission-critical fields for perception tasks. It is therefore vital to analyse the reliability of the designed system before its deployment and, if necessary, to adopt specific hardening techniques. In this paper we propose a cross-layer reliability evaluation framework specifically meant for image processing applications accelerated onto SRAM-based FPGAs. The framework is based on two key concepts: i) an application-level error simulation based on validated error models to speed-up execution times, and ii) an analysis of the usability of the output images based on the working scenario. Such usability analysis allows the designer to study whether the downstream system would be able to take correct decisions even if the image processing outputs are corrupted. We applied the proposed idea on a motion detection application and we compared the achieved accuracy and the required execution times with the ones of a circuit-level fault injector, here considered as a ground truth. This experiment highlighted an accuracy comparable with the one of the fault injection with a dramatic time saving.
Proc. 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
978-1-6654-1609-2
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1210881
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