RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

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Mostrati risultati da 1 a 31 di 31
Titolo Data di pubblicazione Autori File
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions 1-gen-2019 A. BarenghiW. FornaciariA. GalimbertiG. PelosiD. Zoni
Probabilistic-WCET reliability: on the experimental validation of EVT hypotheses 1-gen-2019 Federico ReghenzaniGiuseppe MassariWilliam FornaciariAndrea Galimberti
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 1-gen-2020 Luca CremonaWilliam FornaciariAndrea GalimbertiAndrea RomanoniDavide Zoni
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 1-gen-2021 Giovanni AgostaDaniele CattaneoWilliam FornaciariAndrea GalimbertiGiuseppe MassariFederico ReghenzaniFederico TerraneoDavide ZoniCarlo Brandolese +
An FPU design template to optimize the accuracy-efficiency-area trade-off 1-gen-2021 Davide ZoniAndrea GalimbertiWilliam Fornaciari
On the Effectiveness of True Random Number Generators Implemented on FPGAs 1-gen-2022 Galli, DavideGalimberti, AndreaFornaciari, WilliamZoni, Davide
Cost-effective fixed-point hardware support for RISC-V embedded systems 1-gen-2022 D. ZoniA. Galimberti
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 1-gen-2022 A. GalimbertiD. Zoni +
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 1-gen-2022 Agosta, GiovanniBrandolese, CarloCattaneo, DanieleFornaciari, WilliamGalimberti, AndreaMassari, GiuseppeReghenzani, FedericoTerraneo, FedericoZoni, Davide +
FPGA implementation of BIKE for quantum-resistant TLS 1-gen-2022 Galimberti, AndreaGalli, DavideMontanaro, GabrieleFornaciari, WilliamZoni, Davide
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 1-gen-2022 Montanaro G.Galimberti A.Zoni D. +
On the use of hardware accelerators in QC-MDPC code-based cryptography 1-gen-2022 Galimberti, AndreaGalli, DavideMontanaro, GabrieleFornaciari, WilliamZoni, Davide
A survey on run-time power monitors at the edge 1-gen-2023 Davide ZoniAndrea GalimbertiWilliam Fornaciari
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE 1-gen-2023 Andrea GalimbertiGabriele MontanaroWilliam FornaciariDavide Zoni
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs 1-gen-2023 Galimberti, AndreaMontanaro, GabrieleZoni, Davide
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 1-gen-2023 Fornaciari, WilliamReghenzani, FedericoAgosta, GiovanniZoni, DavideGalimberti, Andrea +
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems 1-gen-2023 Fornaciari W.Agosta G.Cattaneo D.Denisov L.Galimberti A.Magnani G.Zoni D.
FPGA-Based Design and Implementation of a Code-Based Post-quantum KEM 1-gen-2024 Andrea Galimberti
The TEXTAROSSA Project: Cool all the Way Down to the Hardware 1-gen-2024 Agosta, GiovanniCattaneo, DanieleFornaciari, WilliamGalimberti, AndreaLeva, AlbertoReghenzani, FedericoLodi, Carlo SaverioTerraneo, FedericoZoni, Davide +
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA 1-gen-2024 Denisov, LevGalimberti, AndreaCattaneo, DanieleAgosta, GiovanniZoni, Davide
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms 1-gen-2024 Galimberti, AndreaPiccoli, MicheleZoni, Davide
ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring 1-gen-2024 Galimberti, AndreaZoni, DavideFornaciari, William +
Functional ISS-Driven Verification of Superscalar RISC-V Processors 1-gen-2024 Galimberti, AndreaZoni, Davide +
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS 1-gen-2024 Montanaro, GabrieleGalimberti, AndreaZoni, Davide
A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs 1-gen-2025 Galimberti, AndreaMontanaro, GabrieleMotta, AndreaZoni, Davide +
An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research 1-gen-2025 Zoni, DavideGalimberti, AndreaGalli, Davide
Deep Learning on RISC-V Platforms at the Edge: A Perspective on the Hardware and Software Support 1-gen-2025 Agosta, GiovanniGalimberti, AndreaZoni, Davide
Omega: A Hardware-Software Framework for Complete Design Space Exploration of FPGA-Based Heterogeneous Multi-Core SoCs 1-gen-2025 Montanaro, GabrieleGalimberti, AndreaZoni, Davide
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems 1-gen-2025 Davide ZoniAndrea GalimbertiAdriano Guarisco
Mostrati risultati da 1 a 31 di 31
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