In recent years, single-photon timing techniques have been employed in a steadily increasing number of applications. Most of these applications require high detector performance in terms of noise, photon detection efficiency, time resolution, and number of pixels operating in parallel. The detectors best fitting these requirements are single-photon avalanche diode (SPAD) arrays built in custom technology, although the systems based on such detectors are limited to a few pixels. In this paper, we present a novel read-out circuit, developed in a 0.18-μm high voltage-CMOS technology, for the detection of the SPAD avalanche current: the designed circuit is based on a 2.2-GHz bandwidth integrated transimpedance amplifier, followed by a low-pass filter, to reduce crosstalk, and by an integrated comparator. The pick-up circuit has a total power dissipation of 1.1 mW, occupies an overall area of 15,500 μm² and shows a time resolution down to 48 ps and a negligible crosstalk between two different pixels. All these features can open the way to the development of large SPAD arrays, characterized by a performance comparable with that of the single-pixel structures. Moreover, the good agreement between the simulated and the measured resolution (with a 14% maximum error) makes the future improvement of the evaluated performance possible.

A 2-GHz Bandwidth, Integrated Transimpedance Amplifier for Single-Photon Timing Applications

CROTTI, MATTEO CARLO;RECH, IVAN;ACCONCIA, GIULIA;GULINATTI, ANGELO;GHIONI, MASSIMO ANTONIO
2015

Abstract

In recent years, single-photon timing techniques have been employed in a steadily increasing number of applications. Most of these applications require high detector performance in terms of noise, photon detection efficiency, time resolution, and number of pixels operating in parallel. The detectors best fitting these requirements are single-photon avalanche diode (SPAD) arrays built in custom technology, although the systems based on such detectors are limited to a few pixels. In this paper, we present a novel read-out circuit, developed in a 0.18-μm high voltage-CMOS technology, for the detection of the SPAD avalanche current: the designed circuit is based on a 2.2-GHz bandwidth integrated transimpedance amplifier, followed by a low-pass filter, to reduce crosstalk, and by an integrated comparator. The pick-up circuit has a total power dissipation of 1.1 mW, occupies an overall area of 15,500 μm² and shows a time resolution down to 48 ps and a negligible crosstalk between two different pixels. All these features can open the way to the development of large SPAD arrays, characterized by a performance comparable with that of the single-pixel structures. Moreover, the good agreement between the simulated and the measured resolution (with a 14% maximum error) makes the future improvement of the evaluated performance possible.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/985394
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