A Background calibration technique to control bandwidth in digital PLLs

The bandwidth of a phased-locked loop (PLL) is dependent on several analog parameters that are subject to process, temperature and voltage spreads, as well as to variations along the frequency-tuning range. Even in digital PLLs, which rely on a digital loop filter, the bandwidth still depends on the gains of two mixed-signal building blocks, namely the time/digital converter (TDC) and the digitally-controlled oscillator (DCO), that have conversion characteristics that are not well-controlled. The situation is even more cumbersome employing a singlebit TDC, often referred to as bang-bang phase detector (BBPD), where the linearized gain is inversely proportional to the input jitter [1]. An accurate and repeatable value of the PLL bandwidth, and in the general of the frequency response, is essential to meet several specifications, such as stability margin, settling time, jitter and spur level. When the PLL is operated as a direct frequency modulator with pre-emphasis of the modulation signal, the accuracy requirement of the frequency response is even more demanding [2]. Previously disclosed methods to control PLL bandwidth require a modulation signal to be injected into the loop [2], compensate the gain variations of just a single block (e.g., VCO [3] or BBPD [4]), or operate in the foreground [5]. This paper presents a digital PLL employing a digital background normalization of loop gain, which makes it independent of any analog variable (except for the reference frequency, which often is available from an accurate source). This method requires no injection of additional test signals and operates at a low rate, achieving low-noise and low-power operation, and also is suitable even for bang bang PLLs.