On the chapter 6 "Design Time Engineering of Side Channel Resistant Cipher Implementations": Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in the modern information systems. Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show that these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound consevative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched.
Design Time Engineering of Side Channel Resistant Cipher Implementations
BARENGHI, ALESSANDRO;BREVEGLIERI, LUCA ODDONE;PALOMBA, ANDREA;PELOSI, GERARDO
2013-01-01
Abstract
On the chapter 6 "Design Time Engineering of Side Channel Resistant Cipher Implementations": Dependable and trustworthy security solutions have emerged as a crucial requirement in the specification of the applications and protocols employed in the modern information systems. Threats to the security of embedded devices, such as smart phones and PDAs, have been growing since several techniques exploiting side-channel information leakage have proven successful in recovering secret keys even from complex mobile systems. This chapter summarizes the side-channel techniques based on power consumption and elaborates the issue of the design time engineering of a secure system, through the employment of the current hardware design tools. The results of the analysis show that these tools can be effectively used to understand possible vulnerabilities to power consumption side-channel attacks, thus providing a sound consevative margin on the security level. The possible extension of this methodology to the case of fault attacks is also sketched.I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.