A novel design framework for the design of reconfigurable systems based on NoCs

In the last years, the embedded systems market is considerably grown, even though techniques and methodologies for the design of embedded systems, both from the hardware and the software point of view, have not been able to fully support this growth. Within this context, novel methodologies and design flows are required in order both to improve the quality and to shorten the time-to-market of very complex embedded systems. In the above scenario, the main goals of this work are the definition of a novel reconfigurable Network-on-Chip (NoC) architecture characterized by a very high timing performance and a very low area usage, and the development of a framework for the design of Multi-Processor Systems-on-Chip (MPSoCs) based on the proposed NoC. The proposed design flow makes it possible to dynamically adapt and optimize the underlying NoC communication infrastructure to the application that is currently running on the device, even if its communications pattern is not known at design time. In particular, the backbone of the NoC is placed on the static regions, while the computational soft cores of the input applications are partitioned into islands and each island (along with its local portion of the NoC) is automatically mapped by the proposed design flow on a single reconfigurable region. The physical devices used within this work are Xilinx FPGA devices, that allow, thanks to their capabilities of partial dynamic reconfiguration, the design of flexible MPSoCs.