Parallel hardware architectures for the cryptographic Tate pairing

Identity-based cryptography uses pairing functions, which are sophisticated bilinear maps defined on elliptic curves. Computing pairings efficiently in software is presently a relevant research topic. Since such functions are very complex and slow in software, dedicated hard- ware (HW) implementations are worthy of being stud- ied, but presently only very preliminary research is avail- able. This work affords the problem of designing paral- lel dedicated HW architectures, i.e.,co-processors, for the Tate pairing, in the case of the Duursma-Lee algorithm in characteristic 3. Formal scheduling methodologies are applied to carry out an extensive exploration of the archi- tectural solution space, evaluating the obtained structures by means of different figures of merit such as computation time, circuit area and combinations thereof.Comparisons with the (few) existing proposals are carried out, show- ing that a large space exists for the efficient parallelHW computation of pairings.