The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, the regularity and the locality of the interconnections among the adders, have been proposed. The paper affords the introduction of pipelining in these last structures and compares the obtained results with existing structures, in terms of required number of components and operation frequency

Column compression pipelined multipliers

BREVEGLIERI, LUCA ODDONE;DADDA, LUIGI;PIURI, VINCENZO
1995

Abstract

The paper presents a study on the introduction of pipelining in parallel VLSI multipliers, built according to the column compression (CC) design techniques. A number of CC multiplier schemes have been proposed in the literature, aimed at reducing the number of stages of adders necessary to compute a multiplication. More recently CC multiplier schemes aimed at optimising the required silicon area, the regularity and the locality of the interconnections among the adders, have been proposed. The paper affords the introduction of pipelining in these last structures and compares the obtained results with existing structures, in terms of required number of components and operation frequency
Proceedings of the Application Specific Array Processors Conference 1995
0818671092
INF; VLSI; arithmetic; multiplication; multiplier; pipeline architecture
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/569776
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