Aserial multiplication algorithm is discussed and implemented by means of a CMOS technology. AN codes technique is used to allow self-checking of the device and is also implemented. Guidelines to design the test vectors for the device are presented.
Design and implementation of a VLSI serial multiplier for fixed point numbers with self-checking capability
BREVEGLIERI, LUCA ODDONE
1988-01-01
Abstract
Aserial multiplication algorithm is discussed and implemented by means of a CMOS technology. AN codes technique is used to allow self-checking of the device and is also implemented. Guidelines to design the test vectors for the device are presented.File in questo prodotto:
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