A novel convolver is presented in which both samples and results are in serial form, while coefficients are stored in internal registers. The convolver is composed of an array of multiplier-accumulator subunits which operate in a carry-save, serial/parallel mode. The sample bits are broadcast to all subunits, each one executing the multiplication with the stored coefficient and accumulating the product with the result received from the preceding unit. The structure can be shown to be decomposable in bit-slices; a stack of slices can be programmed as a convolver for prescribed sample and coefficient bit-length under the control of a configuration register. Faulty slices can be neutralized by variables stored in a second register.

A serial-input serial-output bit-sliced convolver

BREVEGLIERI, LUCA ODDONE;DADDA, LUIGI
1988-01-01

Abstract

A novel convolver is presented in which both samples and results are in serial form, while coefficients are stored in internal registers. The convolver is composed of an array of multiplier-accumulator subunits which operate in a carry-save, serial/parallel mode. The sample bits are broadcast to all subunits, each one executing the multiplication with the stored coefficient and accumulating the product with the result received from the preceding unit. The structure can be shown to be decomposable in bit-slices; a stack of slices can be programmed as a convolver for prescribed sample and coefficient bit-length under the control of a configuration register. Faulty slices can be neutralized by variables stored in a second register.
1988
Proceedings of the International Conference on Circuit Design
0818608722
INF; VLSI; arithmetic; convolution; convolver
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/569728
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