An encoder/decoder architecture for buses capable of minimizing power consumption by reducing the switching activity.

Encoder architecture for parallel buses

FORNACIARI, WILLIAM;SCIUTO, DONATELLA;SILVANO, CRISTINA;
2001-01-01

Abstract

An encoder/decoder architecture for buses capable of minimizing power consumption by reducing the switching activity.
Computer Architecture; Low-power Design
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/569402
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