A FPGA coprocessor for the cryptographic Tate pairing over Fp

Identity based cryptography offers a number of functional advantages over traditional public key cryptosystems and has attracted much research interest in the last few years. The computational costs demanded for such functionalities result to be significantly greater than those bounded to other methods. The overall efficiency of identity based protocols and applications is dominated by the computation of the main used primitive, namely the Tate pairing. The paper focuses on the design of a parallel hardware accelerator for the computation of the Tate pairing that makes use of arithmetics over finite fields with a large prime characteristic. Performance measurements are discussed and compared with previous solutions based on different definitions and algorithms.