This paper investigates nature and effects of jitter on the clock edge that triggers the sample/hold used in direct-sampling and IF-sampling receiver architectures. The impact of the aperture uncertainty is theoretically discussed, simulated, and measured in the case of the high-frequency front-end of a 16-bit 65 MS/s analog–digital converter. Both characterizations of the phenomenon are considered: in the frequency domain [single-sideband to carrier ratio (SSCR), or phase noise] and in the time domain (aperture jitter).

Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling

SAMORI, CARLO
2008-01-01

Abstract

This paper investigates nature and effects of jitter on the clock edge that triggers the sample/hold used in direct-sampling and IF-sampling receiver architectures. The impact of the aperture uncertainty is theoretically discussed, simulated, and measured in the case of the high-frequency front-end of a 16-bit 65 MS/s analog–digital converter. Both characterizations of the phenomenon are considered: in the frequency domain [single-sideband to carrier ratio (SSCR), or phase noise] and in the time domain (aperture jitter).
2008
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/521130
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