Since standardization in 2001, the Advanced Encryption Standard has been the subject of many research efforts, aimed at developing effcient hardware implementations with reduced area and latency. So far, reliability has not been considered a primary objective. Recently, several error detecting schemes have been proposed in order to provide some defense against hardware faults in AES. The benefits of such schemes are twofold: avoiding wrong outputs when benign hardware faults occur, and preventing the collection of information about the secret key through malicious injection of faults. In this paper, we present a complete scheme for parity-based fault detection in a hardware implementation of the Advanced Encryption Standard which includes a key schedule unit. We also provide a preliminary evaluation of the hardware and latency overhead of the proposed scheme.

An efficient hardware-based fault diagnosis scheme for AES: performances and cost

BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;MAISTRI, PAOLO
2004

Abstract

Since standardization in 2001, the Advanced Encryption Standard has been the subject of many research efforts, aimed at developing effcient hardware implementations with reduced area and latency. So far, reliability has not been considered a primary objective. Recently, several error detecting schemes have been proposed in order to provide some defense against hardware faults in AES. The benefits of such schemes are twofold: avoiding wrong outputs when benign hardware faults occur, and preventing the collection of information about the secret key through malicious injection of faults. In this paper, we present a complete scheme for parity-based fault detection in a hardware implementation of the Advanced Encryption Standard which includes a key schedule unit. We also provide a preliminary evaluation of the hardware and latency overhead of the proposed scheme.
Proceedings of the IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004)
0769522416
9780769522418
INF; cryptography; fault detection; AES cipher; digital circuit; cost evaluation; performance evaluation
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/268598
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