In many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology.

A parallelized design for an elliptic curve cryptosystem coprocessor

BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;SOZZANI, FRANCA;
2005

Abstract

In many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology.
Proceedings of the IEEE Information Technology: Coding and Computing, 2005. ITCC 2005
0769523153
INF; cryptography; digital circuit; parallel architecture; elliptic curve
File in questo prodotto:
Non ci sono file associati a questo prodotto.

I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.

Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/266821
Citazioni
  • ???jsp.display-item.citation.pmc??? ND
  • Scopus 21
  • ???jsp.display-item.citation.isi??? 11
social impact