In many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology.
A parallelized design for an elliptic curve cryptosystem coprocessor
BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;SOZZANI, FRANCA;
2005-01-01
Abstract
In many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology.File in questo prodotto:
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