Concurrent fault detection for hardware implementations of the Advanced Encryption Standard (AES) may provide protection against random faults, and against an attacker who may maliciously inject faults in order to find the encryption secret key. We have recently developed such a scheme which is based on the parity code. In this paper we prove that the parity-based code detects all odd-order faults and allows the location of most single transient and permanent faults.

Detecting and locating faults in VLSI implementations of the advanced encryption standard

BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;MAISTRI, PAOLO;PIURI, VINCENZO
2003

Abstract

Concurrent fault detection for hardware implementations of the Advanced Encryption Standard (AES) may provide protection against random faults, and against an attacker who may maliciously inject faults in order to find the encryption secret key. We have recently developed such a scheme which is based on the parity code. In this paper we prove that the parity-based code detects all odd-order faults and allows the location of most single transient and permanent faults.
Proceedings of the IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003)
0769520421
INF; cryptography; fault detection; fault location; AES cipher; fault attacks; differential fault analysis; digital circuit
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/265941
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