This paper addresses the problem of estimating cost and development effort of a system, starting from its complete or partial high-level description. In addition, some modifications to evaluate the cost-effectiveness of reusing VHDL-based designs, are presented. The proposed approach has been formalized using an approach similar to the COCOMO analysis strategy, enhanced by a project size prediction methodology based on a VHDL function point metric. The proposed design size estimation methodology has been validated through a significant benchmark, the LEON-1 microprocessor, whose VHDL description is of public domain.
|Titolo:||Development Cost and Size Estimation Starting from High-Level Specifications|
|Data di pubblicazione:||2001|
|Appare nelle tipologie:||04.1 Contributo in Atti di convegno|
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|codes2001.pdf||camera ready||Post-print||Accesso riservato|