Low-Power State Assignment Techniques for Finite State Machines

The problem of minimizing the power consumption in synchronous sequential circuits is explored in this paper. We present a general theoretical framework to solve the state assignment problem for Finite State Machines (FSMs). In this framework, the problem has been separated in two different tasks. First, we define heuristic techniques to visit the State Transition Graph (STG) and thus to assign a priority to the symbolic states. Second, we define encoding techniques to assign binary codes to the symbolic states to reduce the switching activity of state registers. Based on this approach, we propose five power-oriented state assignment algorithms. These techniques have been applied to MCNC benchmark circuits and the experimental results have shown an average reduction in transition activity (power) of 8.56% (5.35%) over well-known low-power state encoding schemes