Concurrent fault detection for a hardware implementation of the Advanced Encryption Standard (AES) is important not only to protect the encryption/decryption process from random faults. It will also protect the encryption/decryption circuitry from an attacker who may maliciously inject faults in order to find the encryption secret key. In this paper we present a novel fault detection scheme which is based on a multiple parity bit code and show that the proposed scheme leads to very efficient and high coverage fault detection. We then estimate the associated hardware costs and detection latencies.

A parity code based fault detection for an implementation of the advanced encryption standard

BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;MAISTRI, PAOLO;PIURI, VINCENZO
2002-01-01

Abstract

Concurrent fault detection for a hardware implementation of the Advanced Encryption Standard (AES) is important not only to protect the encryption/decryption process from random faults. It will also protect the encryption/decryption circuitry from an attacker who may maliciously inject faults in order to find the encryption secret key. In this paper we present a novel fault detection scheme which is based on a multiple parity bit code and show that the proposed scheme leads to very efficient and high coverage fault detection. We then estimate the associated hardware costs and detection latencies.
Proceedings of the IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002)
0769518311
INF; cryptography; fault attacks; differential fault analysis; fault detection; parity code; digital circuit
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/259806
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