This work shows a new technique for localizing the position of the weak site responsible for the stress-induced leakage current (SILC) in the tunnel oxide of Flash memories. Reverse biasing the drain-substrate junction during gate-stress results in local modification of the electric field through the oxide, leading to a corresponding change in the local leakage current. Our analysis on selected samples of Flash cells indicates that the SILC-related damage can be partly localized close to the gate-to-drain overlap, indicating that the hot-carrier programming cooperates in the degradation process.

Localization of SILC in Flash memories after program/erase cycling

IELMINI, DANIELE;LACAITA, ANDREA LEONARDO;SOTTOCORNOLA SPINELLI, ALESSANDRO
2002

Abstract

This work shows a new technique for localizing the position of the weak site responsible for the stress-induced leakage current (SILC) in the tunnel oxide of Flash memories. Reverse biasing the drain-substrate junction during gate-stress results in local modification of the electric field through the oxide, leading to a corresponding change in the local leakage current. Our analysis on selected samples of Flash cells indicates that the SILC-related damage can be partly localized close to the gate-to-drain overlap, indicating that the hot-carrier programming cooperates in the degradation process.
40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM
0-7803-7352-9
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/249160
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