Cryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated.
Efficient finite field digit-serial multiplier architecture for cryptography applications
BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;FRAGNETO, PASQUALINA
2001-01-01
Abstract
Cryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated.File in questo prodotto:
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