Cryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated.

Efficient finite field digit-serial multiplier architecture for cryptography applications

BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;FRAGNETO, PASQUALINA
2001

Abstract

Cryptographic applications in embedded systems for smart-cards require low-latency, low-complexity and low power dedicated hardware. In this work the GBB algorithm for finite field multiplication is optimised by recoding and the related digit-serial VLSI multiplier architecture is designed and evaluated.
Proceedings of the Conference on Design Automation and Test in Europe (DATE 2001)
0769509932
9780769509938
INF; cryptography; finite field arithmetic; multiplication; digit-serial multiplier; digital circuit
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/246148
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