A study of UIS ruggedness of mismatched paralleled SiC MOSFETs

This work investigates the ruggedness of paralleled silicon carbide (SiC) MOSFETs tested under unclamped inductive switching (UIS) conditions. More specifically, the maximum avalanche energy (EAV) sustainable by individual and paralleled MOSFETs integrated in a multi-chip power module (PM) is quantified. Circuital electrothermal (ET) simulations are carried out by resorting to a physics-based electrical model of a commercial SiC power MOSFET coupled with a dynamic thermal feedback block (TFB). The electrical model of the power MOSFET, accounting for temperature-sensitive parameters, was calibrated on measurements data of transfer /output characteristics and of UIS tests. The TFB was extracted using FANTASTIC, an advanced numerical tool based on a model-order reduction technique; it accounts for self- and mutual-heating of devices, including nonlinear thermal effects. A comprehensive analysis of the system ruggedness was performed by focusing on (i) mutual heating mechanisms between transistors and (ii) technological mismatches in breakdown voltage (BV).