MEMORY ARCHITECTURES WITH AMBIPOLAR SEMICONDUCTOR CHANNELS

The invention consists of a NAND memory architecture featuring ferroelectric cells integrated within a vertically organized array. The individual cell channels are based on two-dimensional semiconductors, specifically transition metal dichalcogenides, which exhibit significantly better electrical properties compared to polysilicon, the material currently used for similar structures. The ambipolarity of these semiconductors is leveraged to enable fast and efficient memory cell write/erase operations. This architecture allows realizing a Storage technology with a set of value propositions: highly scalable, superior speed performance in Write/Erase and Read operations, low power.