Synthesis of Free-Labeled Petri Nets with Inhibitor Arcs

This paper presents a method for synthesizing a free-labeled Petri net with inhibitor arcs (inhibitor net) from its generated finite language. Inhibitor arcs extend the modeling power of Petri nets to the Turing machine level, offering significant benefits for modeling physical systems such as parallel machine systems in manufacturing. However, inhibitor arcs modify the enabling conditions, complicating the synthesis problem and rendering previous methods inapplicable. To address this challenge, we introduce novel logical conditions to manage the altered enabling conditions and formulate the synthesis problem as an integer linear programming problem. Experimental results demonstrate the effectiveness of the proposed method.