A CMOS Implementation of a Switched Capacitor Analog Neural Network ASIC (ANNA)

We present an implementation of an analog Neural Network (NN) ASIC designed on a CMOS 0.35 μm process node, to be embedded in detector readout with ADC-less and FPGA-less processing.Computations are performed with 5-bit precision in charge domain, by means of charge sharing on programmable switched-capacitors crossbar arrays (which also implements network weights) and charge integration on low-power high-gain operational amplifiers. The NN memory is implemented with SRAM cells, programmed with SPI protocol, and timing events are synchronized with programmable on-chip ring counters driven by an external arbitrary clock. Full circuit simulation has been carried out to evaluate the ASIC performances. The estimated energy consumption to perform an inference is 12 nJ, considering the contribution of components involved in the operations (i.e. capacitors and amplifiers), and the expected energy efficiency is ∼296 GOPs/W. The ASIC is currently in the final design phase and will be soon submitted for fabrication.