This paper presents an analog event processing and acquisition platform, primarily targeting X-ray and electron spectroscopy. It allows the simultaneous acquisition of 48 channels, each one supporting an event rate up to 250 kcps. The main novelty of this version, with respect to a previous implementation named KERBEROS, is the introduction of the timing information in addition to the energy of each detected event. The system is composed of three SFERA-TAC ASICs including a 9 th -order Gaussian shaper with programmable shaping time and a time-to-amplitude converter (TAC) block for each of the 16 channels. The analog outputs (peak energy and time) are multiplexed on-chip at 5 MHz and digitalized off-chip. The FPGA controls the ASICs, produces the timestamps of individual events by combining the TAC values, (relative to clock edges), to the 100 MHz clock cycle, and transfers data to a PC via USB2.0. Experimental results achieved with a 47-pixel monolithic SDD detector developed for the TRISTAN sterile neutrino experiment show the capability of acquiring spectra with state-of-the-art energy resolution, timing linearity (up to 3 µs) of ±1% and temporal resolution of 6 ns FWHM. As example of application enabled by this performance, charge sharing between neighboring detectors is studied and corrected by means of electronic collimation.
KERBEROS-TAC: a 48-Channel Analog Pulse Processor for X-Ray and Beta Spectroscopy
Carminati, Marco;Manfrin, Daniele;King, Pietro;Gugiatti, Matteo;Fiorini, Carlo
2022-01-01
Abstract
This paper presents an analog event processing and acquisition platform, primarily targeting X-ray and electron spectroscopy. It allows the simultaneous acquisition of 48 channels, each one supporting an event rate up to 250 kcps. The main novelty of this version, with respect to a previous implementation named KERBEROS, is the introduction of the timing information in addition to the energy of each detected event. The system is composed of three SFERA-TAC ASICs including a 9 th -order Gaussian shaper with programmable shaping time and a time-to-amplitude converter (TAC) block for each of the 16 channels. The analog outputs (peak energy and time) are multiplexed on-chip at 5 MHz and digitalized off-chip. The FPGA controls the ASICs, produces the timestamps of individual events by combining the TAC values, (relative to clock edges), to the 100 MHz clock cycle, and transfers data to a PC via USB2.0. Experimental results achieved with a 47-pixel monolithic SDD detector developed for the TRISTAN sterile neutrino experiment show the capability of acquiring spectra with state-of-the-art energy resolution, timing linearity (up to 3 µs) of ±1% and temporal resolution of 6 ns FWHM. As example of application enabled by this performance, charge sharing between neighboring detectors is studied and corrected by means of electronic collimation.File | Dimensione | Formato | |
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