Multi-Channel High-Resolution Digital-to-Time Pattern Generator IP-Core for FPGAs and SoCs

In this paper, we present a novel Digital-to-Time Pattern Generator (DTC-PG) IP-Core, capable of generating several high-resolution digital waveforms in parallel, e.g. Pulse Width Modulation (PWM) patterns, compatible with Xilinx 28-nm 7-Series Field-Programmable Gate Array (FPGA) and System-on-Chip (SoC) devices. Compared to the state-of-the-art existing solutions, mainly implemented on Application-Specific Integrated Circuits (ASICs) devices, the advantages of the proposed DTC are the reduced hardware overhead, the high flexibility and, most importantly, reprogrammability, which make our IP-Core portable, more adaptable to different needs and quickly upgradable without the burden of a complete redesign of the system. The DTC output waveforms are tunable at different levels in real-time, and reach excellent performances thanks to the use of dedicated resources, widely available in modern FPGAs, namely Xilinx IDELAYE2/ODELAYE2 primitives. Two different architectures are available, focusing on two different objectives. Both the architectures use a hybrid structure, composed by coarse and fine parts. In this way, it has been possible to generate a variety of waveforms with tens of picosecond resolution and a Full-Scale Range (FSR) in the milliseconds range, maintaining the jitter below a few tens of picoseconds rms. The system is linear within a wide range of input values. The DTC IP-Core is designed for multi-channel solution, a 100-channel version has been successfully validated on a custom board entirely developed at Politecnico di Milano, which hosts a Xilinx Artix-7 XC7A100TFTG256-2.