Nowadays time intervals measurements are the challenges in nuclear electronics, with uncountable applications, like Time-of-Flight Positron Emission Tomography (TOF-PET) and Time-Resolved Spectroscopy. The improvement in temporal resolution of detectors, now up to hundreds of picoseconds, and the increase in the number of channels acquired in parallel, require addressing the research to the design of Time-toDigital Converters (TDC) characterized by a huge number of channels and precision compatible to the jitter of the detector. Furthermore, the requirements of a flexible measurement setup and fast prototyping have focused the design towards fully-digital and all-programmable solutions like Field Programmable Gate Array (FPGA) and System-on-chip (SoC). In this work, we present the design of a low area occupation, pipeline-based, fully-FPGA based Shift-Clock Fast-Counter (SCFC) TDC. In this sense, hundreds of channels can be easily hosted on a small size FPGA; in this structure each channel, equipped with the relative hardware for real-time processing, occupies only 75 SLICEs, of which only 20% are used for the SCFC and its decoding. The SCFC-TDC is characterized by a resolution (LSB) of 156 ps and it has a single-shot channel precision lower than 70 ps r.m.s, over a Full-Scale Range (FSR) extended to some seconds. Furthermore, a differential non-linearity below 0.53 LSB has been measured. The pipeline structure guarantees a maximum measurement rate of 100 Msps, making the device competitive in particle identification experiments. The TDC has been implemented as an IP-Core compatible with 28-nm Xilinx 7-Series FPGAs and SoCs. A user-friendly Graphical User Interface (GUI) helps the user to instantiate the TDC in the design, making also possible the tuning of its parameters, e.g. resolution (LSB), number of channels and Full-Scale Range (FSR). We have tested the proposed solution in two inexpensive and compact FPGA targets: the Artix7 100T and 35T.
High-Channel Count FPGA-based Single-Phase Shift-Clock Fast-Counter Time-to-Digital Converter
Lusardi, N.;Salgaro, S.;Costa, A.;Corna, N.;Garzetti, F.;Ronconi, E.;Geraci, A.
2021-01-01
Abstract
Nowadays time intervals measurements are the challenges in nuclear electronics, with uncountable applications, like Time-of-Flight Positron Emission Tomography (TOF-PET) and Time-Resolved Spectroscopy. The improvement in temporal resolution of detectors, now up to hundreds of picoseconds, and the increase in the number of channels acquired in parallel, require addressing the research to the design of Time-toDigital Converters (TDC) characterized by a huge number of channels and precision compatible to the jitter of the detector. Furthermore, the requirements of a flexible measurement setup and fast prototyping have focused the design towards fully-digital and all-programmable solutions like Field Programmable Gate Array (FPGA) and System-on-chip (SoC). In this work, we present the design of a low area occupation, pipeline-based, fully-FPGA based Shift-Clock Fast-Counter (SCFC) TDC. In this sense, hundreds of channels can be easily hosted on a small size FPGA; in this structure each channel, equipped with the relative hardware for real-time processing, occupies only 75 SLICEs, of which only 20% are used for the SCFC and its decoding. The SCFC-TDC is characterized by a resolution (LSB) of 156 ps and it has a single-shot channel precision lower than 70 ps r.m.s, over a Full-Scale Range (FSR) extended to some seconds. Furthermore, a differential non-linearity below 0.53 LSB has been measured. The pipeline structure guarantees a maximum measurement rate of 100 Msps, making the device competitive in particle identification experiments. The TDC has been implemented as an IP-Core compatible with 28-nm Xilinx 7-Series FPGAs and SoCs. A user-friendly Graphical User Interface (GUI) helps the user to instantiate the TDC in the design, making also possible the tuning of its parameters, e.g. resolution (LSB), number of channels and Full-Scale Range (FSR). We have tested the proposed solution in two inexpensive and compact FPGA targets: the Artix7 100T and 35T.File | Dimensione | Formato | |
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