High-Performance Reconfigurable Digital Instrument for Multi–Channel Time Measurements

A very compact and fully programmable instrument for time measurements at high-performance is presented. The instrument is a complete bundle of hardware, firmware, and software. It consists of a Time-to-Digital Converter (TDC) hosted on a Xilinx 28-nm 7-Series Kintex-7 FPGA. The hardware is composed by two modules on separate PCBs, an analog front-end and a digital processing board. The processing board is the kernel of the design: it hosts the power section and the FPGA that performs the digitization and elaboration of the timestamps and manages the communication with a Personal Computer for the readout. The front-end is, instead, a plug-in board that converts the external time-events into Low-voltage differential signaling (LVDS) signals compatible with the FPGA. In this manner, different front-end modules with different number of channels, i.e. 8 or 16, and architectures, i.e. threshold comparators and constant fraction discriminators, can be interchanged to meet the application requirements. An additional channel is present for synchronization purposes. The FPGA-implemented TDC is based on a Tapped Delay-Line (TDL) architecture, organized as a multi-channel (up to 17 channels) IP-Core; it is capable of generating timestamps with resolution (LSB) of 36.6 fs and precision below 12 ps r.m.s., at an acquisition rate of 50 Msps per channel and with a dead-time below 10 ns for each channel; differential and integral non-linearity errors (DNL and INL) are kept below 0.8 ps and 4 ps respectively. An extremely wide Full-Scale Range (FSR) is guaranteed by the use of Nutt-Interpolation technique.The readout of the measurements is performed by a Personal Computer (PC) through an Universal Serial Bus 3.0 (USB 3.0) connection and a user-friendly software interface. This system is not only customizable from a hardware point of view, but also in terms of firmware and software. Indeed, the user can easily insert custom Hardware Description Language (HDL) modules onto the FPGA or a C++ plug-in for additional needs.