A Drift-Resilient Hardware Implementation of Neural Accelerators Based on Phase Change Memory Devices

Memory devices, such as the phase change memory (PCM), have recently shown significant breakthroughs in terms of compactness, 3-D stacking capability, and speed up for deep learning neural accelerators. However, PCM is affected by the conductance drift, which prevents a precise definition of the synaptic weights in artificial neural networks. Here, we propose an efficient system-level methodology to develop drift-resilient multilayer perceptron (MLP) networks. The procedure guarantees high testing accuracy under conductance drift of the devices and enables the use of only positive weights. We validate the methodology using MNIST, rand-MNIST, and Fashion-MNIST datasets, thus offering a roadmap for the implementation of integrated nonvolatile memory-based neural networks. We finally analyze the proposed architecture in terms of throughput and energy efficiency. This work highlights the relevance of robust PCM-based design of neural networks for improving the computational capability and optimizing energetic efficiency.