This work addresses the reliability of RRAM, with a focus on conductance variation and its impact on in-memory computing (IMC). The core advantage of IMC is the ability to execute matrix-vector multiplication (MVM) in one step in crosspoint memory arrays, which can significantly accelerate data-intensive computing tasks, such as the inference and training of deep neural networks (DNNs). Since MVM is executed in the analogue domain, the imprecision of weight parameters stored in the memory array can result in errors which can affect the accuracy of the computation. By referring to a typical IMC device, that is the resistive switching memory (RRAM), we describe the conductance variations and stability with time, highlighting their impact on IMC accuracy. Then we discuss various options for mapping coefficients in the memory device, including multilevel, binary, unary, redundancy and slicing schemes, and their robustness with respect to conductance errors. It turns out that a tradeoff exists between accuracy and memory area occupation in the IMC circuit. Accurate IMC circuits thus must rely on the co-design of highly-precise, highly-stable devices and error tolerant mapping/computing schemes.

Conductance variations and their impact on the precision of in-memory computing with resistive switching memory (RRAM)

Pedretti G.;Ambrosi E.;Ielmini D.
2021

Abstract

This work addresses the reliability of RRAM, with a focus on conductance variation and its impact on in-memory computing (IMC). The core advantage of IMC is the ability to execute matrix-vector multiplication (MVM) in one step in crosspoint memory arrays, which can significantly accelerate data-intensive computing tasks, such as the inference and training of deep neural networks (DNNs). Since MVM is executed in the analogue domain, the imprecision of weight parameters stored in the memory array can result in errors which can affect the accuracy of the computation. By referring to a typical IMC device, that is the resistive switching memory (RRAM), we describe the conductance variations and stability with time, highlighting their impact on IMC accuracy. Then we discuss various options for mapping coefficients in the memory device, including multilevel, binary, unary, redundancy and slicing schemes, and their robustness with respect to conductance errors. It turns out that a tradeoff exists between accuracy and memory area occupation in the IMC circuit. Accurate IMC circuits thus must rely on the co-design of highly-precise, highly-stable devices and error tolerant mapping/computing schemes.
IEEE International Reliability Physics Symposium Proceedings
978-1-7281-6893-7
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1173656
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