In this contribution we present a new compact, plug-and-play, and user-customizable instrument capable of highperformance Time-to-Digital Conversion (TDC). The instrument features two channels capable of signal timestamping with resolution of 250 ps and precision below 12 ps r.m.s. at an acquisition rate of 50 Msps and dead-time less than 10 ns for each channel. A third input channel is provided for synchronization purposes. The core of the measurement system is a Tapped Delay-Line TDC with sub-interpolation capability, implemented as IP-Core in a Xilinx Artix 7 100T Field-Programmable Gate Array (FPGA). Other IP-cores such as Level-Zero Trigger (LZT),Time-Tagging Module (TTM), Multi-Hits Acquisition (MHA), Hardware Histogram Maker (HHM) are also included and ready to use out of the box. The measurements readout is performed by a Personal Computer (PC) by means of a Universal Serial Bus (USB) connection and a user-friendly software. A novel feature of the described system is the customizable nature of the instrument and its associated software. The IP-Core composition of the firmware makes it more flexible with respect to a standard Hardware Description Language (HDL) code and leaves the possibility to easily add user-made modules, to accommodate for advanced and application-specific measurements without affecting the TDC performance.

Ultra-Compact and User-Customizable Instrument for Time Measurements at High-Performance

F. Garzetti;N. Lusardi;N. Corna;S. Salgaro;G. Locri;A. Geraci
2020-01-01

Abstract

In this contribution we present a new compact, plug-and-play, and user-customizable instrument capable of highperformance Time-to-Digital Conversion (TDC). The instrument features two channels capable of signal timestamping with resolution of 250 ps and precision below 12 ps r.m.s. at an acquisition rate of 50 Msps and dead-time less than 10 ns for each channel. A third input channel is provided for synchronization purposes. The core of the measurement system is a Tapped Delay-Line TDC with sub-interpolation capability, implemented as IP-Core in a Xilinx Artix 7 100T Field-Programmable Gate Array (FPGA). Other IP-cores such as Level-Zero Trigger (LZT),Time-Tagging Module (TTM), Multi-Hits Acquisition (MHA), Hardware Histogram Maker (HHM) are also included and ready to use out of the box. The measurements readout is performed by a Personal Computer (PC) by means of a Universal Serial Bus (USB) connection and a user-friendly software. A novel feature of the described system is the customizable nature of the instrument and its associated software. The IP-Core composition of the firmware makes it more flexible with respect to a standard Hardware Description Language (HDL) code and leaves the possibility to easily add user-made modules, to accommodate for advanced and application-specific measurements without affecting the TDC performance.
2020
2020 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2020
978-1-7281-7693-2
Time-to-Digital Converter (TDC), IP-Core, Field-Programmable Gate Array (FPGA), Level-Zero Trigger (LZT), Time-Tagging Module (TTM), Multi-Hits Acquisition (MHA), Hardware Histogram Maker (HHM), Personal Computer (PC), Universal Serial Bus (USB), Hardware Description Language (HDL)
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1169743
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