Implementation Issues of a High-Performance Multi-Channel Time-to-Digital Converter in Xilinx 20-nm UltraScale FPGAs

In this contribution we discuss implementation issues of a resource-saving, multi-channel, high-performance, Time-to-Digital Converter (TDC) based on Tapped Delay-Line (TDL) designed for implementation in Xilinx 20-nm UltraScale Field Programmable Gate Array (FPGA) devices.Principal features of the system are to be multi-channel, resolution (LSB) of 100 fs, and full-scale range of 419 μs.Each channel measures 32-bit timestamps by means of the Nutt-interpolation, i.e. merging a coarse with a fine part of the measure. For each channel, the coarse contribution is obtained by sampling an 18-bit counter clocked at 625 MHz, whereas the fine one is returned by the interpolation of 16 TDLs.