Hardware Description Language Phase-Locked Loop (HDL-PLL) Open Architecture for FPGAs

This contribution aims to be a proof of the feasibility of a fully open architecture in Hardware Description Language of a Phase-Locked Loop (HDL-PLL) implemented in Field Programmable Gate Array (FPGA).Main parts of the system are the Phase-Frequency Detector (PFD) based on a Time-to-Digital Converter (TDC) and the Digital-Controlled Oscillator (DCO).Both of them are implemented by means of asynchronous architectures making possible to tune the DCO output period, by means of a feedback loop, with resolution of 78 ps and cycle-cycle jitter below 75.3 ps r.m.s.The dynamic range of the HDL-PLL is set by the user during the implementation and varies from several hundreds of MHz with no practical lower limit.